1. Field of the Invention
This invention relates in general to semiconductor processing and more specifically to conductive via formation utilizing electroplating.
2. Description of the Related Art
Semiconductor devices utilize through substrate electrical connections for transferring signals, power, and/or ground through a substrate. In one example, such connections may be utilized for transferring signals between integrated circuits in a multi integrated circuit package. In another example, a through substrate connection may be utilized as a ground connection for grounding a circuit to a package substrate. Such through substrate connections may be desirable because they are typically shorter and have less resistance and inductance than a wire bond connection.
Some through substrate connections are made by forming a conductive via through a substrate from the backside of a wafer to a contact pad of an interconnect layer. In one method of forming a conductive via through a substrate, a conformal seed layer is formed from the backside of the wafer. This seed layer is then used as a cathode for electroplating from the backside of the wafer. One problem with this method is that forming the seed layer in a through substrate via with a high aspect ratio can be difficult due to the limitations of sputtering and other deposition processes. Also, during the electroplating of copper, pinch off may occur, especially near the backside opening of high aspect ratio vias, that result in voids in the conductive filler material. Another problem is that because the seed layer is formed over the entire surface of the backside of the wafer, the via filler material is also formed on the entire surface of the wafer. Such material may have to be subsequently removed.
Another method for via formation through a substrate involves etching a via opening through an entire wafer. A seed layer is then sputtered on the backside of the wafer in such a manner as to be sufficiently thick to close the via off from the backside. A conductive filler material is then deposited from the front side of the wafer by electroplating. One problem with this method is that vias must be formed through the entire wafer. Also, the bottom seed layer would have to be removed or patterned after via filling. Removal or patterning of such a thick metal layer may be complex, difficult to control, and/or time consuming. Furthermore, the conductive filler material does not form a connection to a pre-existing electrical interconnect of the circuit. Thus additional processing must be performed to connect the filled via to circuit elements on the front side of the wafer. This additional processing would be performed on a thinned wafer where wafer thinning is done prior to through wafer via formation.
What is desired is an improved technique for forming a conductive via through a substrate.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.